The present disclosure relates generally to systems and method for monitoring semiconductor wafer fabrication, for example by inspection of an edge exclusion zone of a wafer, including optimization fabrication process steps.
Over the past several decades, semiconductor-driven technologies have grown exponentially and have revolutionized our society. Manufacturers of semiconductors have made vast improvements in production, resulting in improved end product quality, speed, and performance. However, there continues to be demand for faster, more reliable, and higher performing semiconductors. To assist with these demands, better monitoring and/or inspection systems and methods are continuously being sought.
For reference, semiconductors are often manufactured in wafer format, with each wafer including a series of layers, including, for example, a silicon and insulator layer or layers in a silicon-on-insulator or SOI wafer. Regardless, during wafer production, masking layers or resist layers are often times applied to a wafer in order to facilitate wafer patterning. Typically, a desired amount of liquid resist is applied to a top surface of a wafer while the wafer is being rotated. As the wafer is rotated, the resist material spreads outward radially from the center of the wafer and toward the semiconductor edge such that the wafer is substantially coated with a circular layer of resist. Excess amounts of resist can accumulate and form a mound or bead of resist toward an outer edge of the semiconductor wafer. At times, the resist also flows over the wafer edge, which can contaminate an edge normal and a backside of the wafer. Various edge bead removal (EBR) processes are applied in order to eliminate the “edge bead” of resist and/or other unwanted material proximate the wafer edge.
It is also noted that during wafer production, various material removal processes are employed, including, for example, wet etches, a dry etches, polishing, chemical mechanical polishing (CMP), and others depending on the materials being removed. During EBR removal, for example, chemical EBR units remove a ring of resist and other unwanted material about the edge of the wafer by dispensing a solvent referred to as EBR fluid, onto the resist of the semiconductor wafer. The solvent dissolves or develops away the resist and allows for easy removal of the resist from the edge of the semiconductor wafer. Wafer edge exposure (WEE) units can be additionally or alternatively applied for EBR purposes. WEE utilizes an optical unit to expose a ring of resist at or near the edge of the semiconductor wafer to light. During subsequent development processes, the exposed ring of resist is removed.
Accurate placement of the edge exclusion region is critical to maintaining edge die yield. Variation in film overlay in the edge exclusion region can lead to yield-limiting defects. Edge Bead Removal (EBR) metrology or Edge Exclusion Width (EEW) metrology describes a topside surface measurement of the wafer edge exclusion region relative to the wafer center and the wafer edge. This measurement is typically made at several points along the wafer's edge and often ranges between 0 mm and 6 mm in width. In photolithography, EBR metrology data can be used to determine the repeatability of wafer alignment and the accuracy of EBR dispensing nozzles on the coat track.
In addition to EBR/EEW metrology, wafer edge inspection provides an indirect method to control the EBR process by detecting jaggedness of the EBR profile, scalloping, splashing, and other EBR line defects. Improper EBR can also create residuals on other edge surfaces that can lead to cross-contamination of wafers and handling equipment.
The EBR process is used directly after resist coating to remove excess photo resist around the perimeter of the wafer at a fixed distance from the wafer edge. The edge exclusion region can be created in two ways. In a chemical EBR process, a solvent is dispensed in this area as the wafer rotates to create an edge exclusion region. An optical EBR is created during wafer exposure by also exposing the photo resist around the perimeter of the wafer.
The EBR process is often overlooked as a mechanism that can cause front side damage. This is because EBR metrology (the ability to determine if the EBR is too big, too small, off-center, etc.) is still a manually intensive step in modern fabs. The most common method to measure EBR dimensions is to place the wafer onto an optical microscope and measure the distance from the EBR line to the wafer edge at three or more positions around the wafer.
This manual-type EBR measurement approach is oftentimes performed using a manual profiler that is also used to measure trench depths. The tool works by dragging a stylus across the wafer from the center outward. To measure EBR, the distance (measurement #1) is recorded from some reference point to the point where the stylus drops down from the resist height to the bare wafer where the EBR begins. The distance from the same reference point to the point where the stylus falls off the edge of the wafer (measurement #2) is also recorded. EBR width is calculated by subtracting measurement #1 from measurement #2. These measurements are taken at 3 points around the wafer, 120 degrees apart, as reflected in FIG. 1.
EBR measurements taken on the profiler can be susceptible to error. The tool is very sensitive to vibration, which can often result in false readings. The stylus can also give inaccurate readings on non-uniform wafer topography, requiring additional measurements. This process is time consuming, as it can take up to 10 minutes to measure 2 wafers using this method.
This manual approach can also be problematic for several other reasons. First, the wafer bevel transition can easily be mistaken for the wafer edge apex, leading to a smaller Edge Exclusion Width (EEW) measurement, thus compromising the integrity of the data. Secondly, the EBR line can be difficult to distinguish on patterned wafers, especially when some layers are patterned all the way to the edge. Additionally, the EBR line may be discontinuous around the wafer leading to erroneous measurement; and finally, three measurement points per wafer is insufficient to statistically represent the EBR characteristics of a wafer.
Manual EBR metrology is generally reserved for preventive maintenance using test wafers. As a result, infrequent sampling allows out-of-spec EBR to go unnoticed. Out of spec or off-center EBR can result in several different process-related issues. If the EBR width is too narrow, edge grippers on process tools can touch the hardened, brittle photoresist and cause it to crack and flake off, causing contamination. If the edge exclusion is too wide, there will be less surface area available for product die. The ITRS roadmap previously called for an edge exclusion of 2 mm. In 2007, this value changed to 1.5 mm to tie in with the 65 nm node.
Poor control of the Edge Bead Removal process leads to poor edge die yield. EBR control and accuracy are important with multiple stacked layers. If EBR is off-center, undercutting of films can lead to popping at the edge. Additionally, there is a correlation between out-of-spec EBR metrology and edge film adhesion. For example, an off-centered EBR indicates that part of the wafer edge is under-cleaned. A larger-than-usual EBR may indicate an edge “overhang” problem in a film stack. Unwanted film geometry along the wafer edge can cause unexpected film stress and reduce film adhesion to the substrate, resulting in delamination and flaking These defects can then be transferred to the front side of the wafer. This is particularly crucial in metal CMP where the delaminated metal flakes can move from the wafer edge and lodge between the polishing pad and the front surface of the wafer, causing severe front side scratches during the polishing step. If an EBR excursion is not detected in a timely manner, product may need to be reworked or scrapped.
In light of the above, a need exists for semiconductor fabrication monitoring systems and methods that rapidly and accurately characterize EBR-related feature(s), and implement, where necessary, alterations to the fabrication processing steps.